The Advantages and Disadvantages of RISC and CISC

The Advantages of RISC architecture

• RISC(Reduced instruction set computing)architecture has a set of instructions, so high-level language compilers can produce more efficient code
• It allows freedom of using the space on microprocessors because of its simplicity.
• Many RISC processors use the registers for passing arguments and holding the local variables.
• RISC functions use only a few parameters, and the RISC processors cannot use the call instructions, and therefore, use a fixed length instruction which is easy to pipeline.
• The speed of the operation can be maximized and the execution time can be minimized.
  Very less number of instructional formats, a few numbers of instructions and a few addressing modes are needed.

The Disadvantages of RISC architecture

• Mostly, the performance of the RISC processors depends on the programmer or compiler as the knowledge of the compiler plays a vital role while changing the CISC code to a RISC code
• While rearranging the CISC code to a RISC code, termed as a code expansion, will increase the size. And, the quality of this code expansion will again depend on the compiler, and also on the machine’s instruction set.
• The first level cache of the RISC processors is also a disadvantage of the RISC, in which these processors have large memory caches on the chip itself. For feeding the instructions, they require very fast memory systems.

Advantages of CISC architecture

• Microprogramming is easy assembly language to implement, and less expensive than hard wiring a control unit.
• The ease of microcoding new instructions allowed designers to make CISC machines upwardly compatible:
• As each instruction became more accomplished, fewer instructions could be used to implement a given task.

Disadvantages of CISC architecture

• The performance of the machine slows down due to the amount of clock time taken by different instructions will be dissimilar
• Only 20% of the existing instructions is used in a typical programming event, even though there are various specialized instructions in reality which are not even used frequently.
• The conditional codes are set by the CISC instructions as a side effect of each instruction which takes time for this setting – and, as the subsequent instruction changes the condition code bits – so, the compiler has to examine the condition code bits before this happens.